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INTEGRATED CIRCUITS
DATA SHEET
TDA8586 Power amplifier with load detection and auto BTL/SE selection
Preliminary specification Supersedes data of 1998 May 25 File under Integrated Circuits, IC01 1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
FEATURES General * Operating voltage from 8 to 18 V * Low distortion * Few external components, fixed gain * Automatic mode selection (SE or BTL) depending on connected `rear' loads * Can be used as a stereo amplifier in Bridge-Tied Load (BTL) or quad Single-Ended (SE) amplifiers * Single-ended mode without loudspeaker capacitor * Soft clipping, to guarantee good clip behaviour with inductive loads * Mute and standby mode with one-pin operation * Diagnostic information for Dynamic Distortion Detector (DDD), high temperature (140 C) mode of operation and short-circuit * No switch-on/off plops when switching between standby and mute and from mute to on * Load detection on `rear' channels when switching from standby to mute * Fast mute on supply voltage drops (low VP mute). Protection * Short-circuit proof to ground, positive supply voltage on all pins and across load * ESD protected on all pins * Thermal protection against temperatures exceeding 150 C * Load dump protection * Overvoltage protection. ORDERING INFORMATION TYPE NUMBER TDA8586Q TDA8586TH PACKAGE NAME DBS17P HSOP20 DESCRIPTION plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) heatsink small outline package; 20 leads; low stand-off GENERAL DESCRIPTION
TDA8586
The IC incorporates the following functions: 1. 4 x 6 W SE amplifies without SE capacitor, because of the availability of 2 half supply voltage power buffers 2. 2 x 20 W BTL amplifiers 3. Automatic switching between 2 and 4 speaker operation. The mode of operation is determined during start-up. This amplifier is protected for all general short-circuit conditions to battery or ground, overvoltage, 45 V load dump and short-circuits on the speaker outputs. The IC is contained in a 20-pin power HSOP package, but is also available in a 17-pin SIL power package. When packaged in the 20-pin HSOP package additional functions are available: 1. DDD level selection between 2 and 10% 2. Overrule pin for changing mode of operation (from SE to BTL or from BTL to SE).
VERSION SOT243-1 SOT418-2
1999 Apr 08
2
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
QUICK REFERENCE DATA SYMBOL VP Iq(tot) Istb Gv PARAMETER operating supply voltage total quiescent current standby supply current voltage gain VP = 14.4 V, SE mode VP = 14.4 V SE mode BTL mode Bridge-tied load application Po output power VP = 14.4 V; RL = 4 THD = 0.5% THD = 10% THD VOO total harmonic distortion DC output offset voltage fi = 1 kHz; Po = 1 W; VP = 14.4 V; RL = 4 VP = 14.4 V; RL = 4 ; mute condition VP = 14.4 V; on condition Vn(o) Po noise output voltage Rs = 1 k; VP = 14.4 V VP = 14.4 V; RL = 4 THD = 0.5% THD = 10% THD VOO total harmonic distortion DC output offset voltage fi = 1 kHz; Po = 1 W; VP = 14.4 V; RL = 4 VP = 14.4 V; RL = 4 ; mute condition VP = 14.4 V; on condition Vn(o) noise output voltage Rs = 1 k; VP = 14.4 V 4 5 - - - - 4.5 6 0.08 10 0 80 - - Single-ended application output power 14 17 - - - - 15 21 0.05 10 0 100 - - CONDITIONS - - 25 31 MIN. 8.0 - 140 1 26 32 TYP.
TDA8586
MAX. 18 170 100 27 33 V
UNIT mA A dB dB
W W % mV mV V
0.15 20 100 200
W W % mV mV V
0.15 20 100 150
1999 Apr 08
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Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
BLOCK DIAGRAM
TDA8586
handbook, full pagewidth
VP1 2 IN1 5 60 k
VP2 16
-
V/I
-
OA
+ + +
1
OUT1
TDA8586Q
60 k
V/I
-
VPn OA
-
3
HVP1
+
IN2
6 60 k
+ +
V/I OA
4
OUT2
-
- -
IN3
7 60 k
V/I
-
OA
+ + +
17
OUT3
ACREF
11
VPn 30 k
60 k
V/I
-
VPn OA
-
15
HVP2
+
BUFFER 8 60 k
+ +
V/I OA
IN4
14
OUT4
-
-
MSO
13
INTERFACE
DIAGNOSTIC
12
DIAG
10 PGND2
9
MGR023
PGND1
Fig.1 Block diagram SOT243-1.
1999 Apr 08
4
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
handbook, full pagewidth
VP1 18 IN1 2 60 k
VP2 13
-
V/I
-
OA
+ + +
17
OUT1
TDA8586TH
n.c. 1
60 k
V/I
-
VPn OA
-
19
HVP1
+
IN2
3 60 k
+ +
V/I OA
20
OUT2
-
- -
IN3
4 60 k
V/I
-
OA
+ + +
14
OUT3
ACREF
6
VPn 30 k
60 k
V/I
-
VPn OA
-
12
HVP2
+
BUFFER 5 60 k
+ +
V/I OA
IN4
11
OUT4
-
-
MSO
8
INTERFACE
DIAGNOSTIC
7
DIAG
10 DDDSEL
9 OVERRULE
15 PGND2
16
MGR024
PGND1
Fig.2 Block diagram SOT418-2 (HSOP20 heatsink up).
1999 Apr 08
5
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
PINNING SYMBOL n.c. IN1 IN2 IN3 IN4 ACREF DIAG MSO OVERRULE DDDSEL OUT4 HVP2 VP2 OUT3 PGND2 PGND1 OUT1 VP1 HVP1 OUT2 PIN SOT243 - 5 6 7 8 11 12 13 - - 14 15 16 17 10 9 1 2 3 4 PIN SOT418 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 not connected non-inverting input 1 inverting input 2 non inverting input 3 inverting input 4 common signal input diagnostic output/mode fix mode select mute, standby or on mode selection overrule DESCRIPTION
TDA8586
2 or 10% dynamic distortion detection SE output 4 (negative) buffer output/BTL output 2 (negative) supply voltage 2 SE output 3/BTL output 2 (positive) power ground 2 power ground 1 SE output 1/BTL output 1 (positive) supply voltage 1 buffer output/BTL output 1 (negative) SE output 2 (negative)
1999 Apr 08
6
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
handbook, halfpage
OUT1 VP1 HVP1 OUT2 IN1 IN2 IN3 IN4 PGND1
1 2 3 4 5 6 7 8 9
handbook, halfpage
n.c. 1 IN1 2 IN2 3 IN3 4 IN4 5
20 OUT2 19 HVP1 18 VP1 17 OUT1 16 PGND1
TDA8586Q
TDA8586TH
ACREF 6 DIAG 7 MSO 8 OVERRULE 9 DDDSEL 10
MGR026
15 PGND2 14 OUT3 13 VP2 12 HVP2 11 OUT4
PGND2 10 ACREF 11 DIAG 12 MSO 13 OUT4 14 HVP2 15 VP2 16 OUT3 17
MGR025
Fig.3 Pin configuration (SOT243-1).
Fig.4 Pin configuration (SOT418-2).
1999 Apr 08
7
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
FUNCTIONAL DESCRIPTION The TDA8586 is a multi-purpose power amplifier with four amplifiers and 2 buffer stages, which can be connected in the following configurations with high output power and low distortion: * Dual Bridge-Tied Load (BTL) amplifiers * Quad Single-Ended (SE) amplifiers. In the BTL mode of operation, the 2 buffer amplifiers act as inverting amplifiers to complete the bridge across the `front' amplifiers (OUT1 and OUT3) and the `rear' outputs (OUT2 and OUT4) enter a high-impedance state. In the SE mode of operation, the buffers act as an AC ground path thereby eliminating the need for series capacitors on the speaker outputs. Diagnostics: * While the IC is in the mute mode, the diagnostic output will signal the mode of operation when the IC is not overruled * In the on mode the diagnostic output will signal any fault in the IC or if the output of any amplifier is clipping with a distortion of 10% (or 2% depending on selected clip-mode). Special attention is given to the dynamic behaviour as follows: * Noise suppression during engine start * No plops when switching from standby to on * Slow offset change between mute and on (controlled by MSO pin) * Low noise levels, which are independent of the supply voltage. Protections are included to avoid the IC being damaged at: * Over temperature: Tj > 150 C * Short-circuit of the output pin(s) to ground or supply rail. When short-circuited, the power dissipation is limited * ESD protection (Human Body Model 3000 V and Machine Model 300 V).
TDA8586
The presence of the load is measured after the transition between standby and mute. The IC will determine if there is an acceptable load on both outputs (OUT2 and OUT4). If both outputs are unloaded, the IC will switch to a 2 speaker mode of operation (BTL mode), unless it is overruled. There are two options to overrule: 1. Before transition from mute to on, after a load detection, pulling the diagnostic output above 9.5 V will force the IC into 4 speaker mode 2. TDA8586TH: pulling the OVERRULE pin according pinning table. Care should be taken with the OVERRULE function as it works during the on mode. If there is a 2 or 4 speaker mode change during the on mode a large `plop' can be heard on the speakers. The ACREF input (common signal input) acts with the four signal inputs (IN1 to IN4) to provide quasi differential inputs. A capacitor must be connected to this pin of which the ground pin should be connected to the ground at the signal source (usually the ground at the audio signal processor). This capacitor has a dual function. During the speaker detection, the signal ground capacitor is used to set the time constant of the measurement (and thus determines the minimum required switch-on time). The capacitor on the MSO pin allows the integrate function to provide immunity to outside noises during load detection.
1999 Apr 08
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Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
handbook, full pagewidth
state condition
standby
mute load detect
mute no load detect
on no clipping/shorts
on clipping
on short-circuit
VP VP 0 minimum 1 s 9V MSO SE detection
3V 0
BTL detection
5V diagnostic information 0
BTL detected
SE detected
10 V diagnostic overrule 0 5V mode select 0
The mode is overruled only from BTL to SE when the diagnostic pin is excited with a pulse of 10 V.
This voltage must remain present. Whatever the load detection has found the mode of operation will be inverted. Toggling between the 2 modes is possible.
short-circuit to supply
amplifier output
0.5VP 0
short-circuit over load
short-circuit to ground
short-circuit to supply short-circuit over load
0.5VP buffer/amplifier output 0
short-circuit to ground
MGR027
Fig.5 Timing diagram including diagnostics.
1999 Apr 08
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Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP supply voltage PARAMETER CONDITIONS operating load dump protected; see Fig.6 VDIAG IOSM IORM Vrp Vsc Ptot Tj Tstg Tamb Note 1. A large reverse current will flow, therefore external protection is needed (fuse and reverse diode). voltage on diagnostic pin non-repetitive peak output current repetitive peak output current reverse polarity voltage AC and DC short-circuit voltage of output pins across loads and to ground or supply pins total power dissipation junction temperature storage temperature operating ambient temperature note 1 8 - - - - - - - - -55 -40 MIN.
TDA8586
MAX. 18 45 18 6 4 6 18 75 150 +150 +150 V V V A A V V W
UNIT
C C C
handbook, halfpage
MGL404
45 V
VP 14.4 V
tr
tf
t (ms)
Fig.6 Load dump voltage waveform.
THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Rth(j-c) PARAMETER thermal resistance from junction to ambient thermal resistance from junction to case CONDITIONS in free air VALUE 40 2 UNIT K/W K/W
1999 Apr 08
10
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
CHARACTERISTICS VP = 14.4 V; Tamb = 25 C; fi = 1 kHz; RL = ; measured in test circuit of Fig.8; unless otherwise specified. SYMBOL Supplies VP Iq(tot) Istb VO VP(mute) Vo operating supply voltage total quiescent current standby current DC output voltage low supply voltage mute single-ended and bridge-tied load output voltage VP = 14.4 V; RL = 4 mute condition on condition VI PIN MSO VMSO voltage at pin MSO standby condition mute condition; note 1 on condition IMSO input current mute pin at standby condition; VMSO < 0.8 V 0 2.0 8.0 - - 3.0 - 5 0.8 4 10.5 40 V V V A DC input voltage VP = 14.4 V - - - - - 4.0 20 100 - mV mV V VP = 14.4 V SE mode 8.0 - - - 6.0 14.4 140 1 7.0 7.0 18 170 100 - 8.0 V mA A V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Diagnostic; output buffer (open-collector); see Figs 7 to 8 VDIAG(L) ILI VDIAG(or) VDIAG(4ch) CD2 CD10 diagnostic output voltage LOW Isink = 1 mA leakage current diagnostic override voltage VDIAG = 14.4 V in mute mode after load detection - - 10.5 - 0.5 7 0.3 - - 0.3 2 10 0.8 1 18 0.8 3.5 13 V A V V % %
diagnostic 4 channel indication mute, after load detection with voltage 4 speakers connected clip detector LOW clip detector HIGH THD mode; VDIAG > 3 V; R = 10 k THD mode (default); VDIAG > 3 V; R = 10 k 10% DDD 2% DDD VDDDSEL = 5 V
CLIP DETECT CONTROL PIN VDDDSEL IDDDSEL voltage at DDD select pin to obtain: Input current DDD select pin 0 3 15 - - - 1 6 140 V V A
1999 Apr 08
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Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
SYMBOL PARAMETER CONDITIONS fi = 1 kHz; Po = 1 W; RL = 4 45 Hz < fi < 10 kHz; Po = 1 W; RL = 4 ; filter: f < 30 kHz Po output power VP = 14.4 V; RL = 4 ; note 2 THD = 0.5% THD = 10% Gv Gv cs VOO voltage gain channel unbalance channel separation DC output offset voltage Vi(rms) = 15 mV Vi(rms) = 15 mV Po = 2 W; fi = 1 kHz; RL = 4 VP = 14.4 V; on condition VP = 14.4 V; RL = 4 ; mute condition Vn(o) Vn(o)(mute) Vo(mute) SVRR noise output voltage on noise output voltage mute output voltage mute Rs = 1 k; VP = 14.4 V; note 3 note 3 Vi(rms) = 1 V 14 17 31 -0.7 45 - - - - - 15 21 32 0 55 0 10 100 0 3 - - - - MIN. TYP.
TDA8586
MAX.
UNIT
Stereo BTL application (see Fig.7) THD total harmonic distortion 0.05 0.3 0.15 - % %
W W dB dB dB mV mV V V V
33 +0.7 - 100 20 150 20 500
supply voltage ripple rejection: Rs = 0 ; fi = 1 kHz; Vripple = 2 V (p-p) on condition mute condition 45 55 40 55 70 60 - - 90 dB dB k
Zi
input impedance
input referenced to ground
1999 Apr 08
12
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
SYMBOL PARAMETER CONDITIONS fi = 1 kHz; Po = 1 W; RL = 4 45 Hz < fi < 10 kHz; Po = 1 W; RL = 4 ; filter: f < 30 kHz Po output power VP = 14.4 V; RL = 4 ; note 2 THD = 0.5% THD = 10% Gv Gv cs VOO voltage gain channel unbalance channel separation DC output offset voltage Vi(rms) = 15 mV Vi(rms) = 15 mV Po = 2 W; fi = 1 kHz; RL = 4 VP = 14.4 V; on condition VP = 14.4 V; RL = 4 ; mute condition Vn(o) Vn(o)(mute) Vo(mute) SVRR noise output voltage on noise output voltage mute output voltage mute supply voltage ripple rejection Rs = 1 k; VP = 14.4 V; note 3 note 3 Vi(rms) = 1 V Rs = 0 ; fi = 1 kHz; Vripple = 2 V (p-p) on condition mute condition Notes 43 55 47 70 - - 4 5 25 -0.7 40 - - - - - 4.5 6 26 0 50 0 10 80 0 3 - - - - MIN. TYP.
TDA8586
MAX.
UNIT
Quad SE application (see Fig.8) THD total harmonic distortion 0.05 0.5 0.15 - % %
W W dB dB dB mV mV V V V
27 +0.7 - 100 20 150 20 500
dB dB
1. Tolerances on the mute level is tight because of the usage of this pin for integration during load detection. 2. The output power is measured directly on the pins of the IC. 3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz.
1999 Apr 08
13
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
APPLICATION INFORMATION
TDA8586
handbook, full pagewidth
1000 F (16/40 V) VP1 2 220 nF IN1 5 60 k VP2 16
100 nF
VP
-
V/I
VINL front
-
OA
+ +
1 OUT1
+ + TDA8586Q
60 k V/I
- -
VPn OA 3 HVP1
4 or 8
-
+
220 nF
IN2 6 60 k
+ +
V/I OA
4 OUT2
-
- -
220 nF VINR front
IN3 7 60 k
V/I
-
OA
+ + +
17 OUT3
ACREF 11 47 F (10 V) VPn 30 k 60 k
+ -
4 or 8
V/I
-
VPn OA
-
15 HVP2
+
BUFFER 220 nF IN4 8 60 k
+ +
V/I OA
14 OUT4
switched +9 V 30 k MSO 13 15 k switch 4.7 F (10 V) 10 INTERFACE
-
+5 V 10 k DIAGNOSTIC 9 PGND1
MGR028
-
12 DIAG
PGND2
Fig.7 Stereo bridge-tied load application (SOT243-1).
1999 Apr 08
14
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
handbook, full pagewidth
1000 F (16/40 V) VP1 2 220 nF IN1 5 60 k VP2 16
100 nF
VP
-
V/I
VINL front
-
OA
+ +
1 OUT1
+ + TDA8586Q
60 k V/I
- -
VPn OA 3 HVP1
4 or 8
-
+
+ -
OA 4 OUT2
4 or 8
220 nF VINL rear
IN2 6 60 k
+ +
V/I
-
- -
220 nF VINR front
IN3 7 60 k
V/I
-
OA
+ + +
17 OUT3
ACREF 11 47 F (10 V) VPn 30 k 60 k
+ -
4 or 8
V/I
-
VPn OA
-
15 HVP2
+
+ -
OA 14 OUT4
BUFFER 220 nF VINR rear switched +9 V 30 k MSO 13 IN4 8 60 k
4 or 8
+ +
V/I
-
+5 V 10 k
-
INTERFACE 10 9
DIAGNOSTIC
12 DIAG
15 k switch 4.7 F (10 V)
PGND2
PGND1
MGR029
Fig.8 Quad single-ended application (SOT243-1).
1999 Apr 08
15
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
handbook, full pagewidth
1000 F (16/40 V) VP1 18 220 nF IN1 2 60 k VP2 13
100 nF
VP
-
V/I
VINL front
-
OA
+ +
17 OUT1
+ + TDA8586TH
n.c. 1 60 k V/I
- -
VPn OA 19 HVP1
4 or 8
-
+
220 nF
IN2 3 60 k
+ +
V/I OA
20 OUT2
-
- -
220 nF VINR front
IN3 4 60 k
V/I
-
OA
+ + +
14 OUT3
ACREF 6 47 F (10 V) VPn 30 k 60 k
+ -
4 or 8
V/I
-
VPn OA
-
12 HVP2
+
BUFFER 220 nF IN4 5 60 k
+ +
V/I OA
11 OUT4
switched +9 V 30 k MSO 8 15 k switch 4.7 F (10 V) 10 DDDSEL 9 INTERFACE
-
+5 V 10 k DIAGNOSTIC 15 PGND2 16 PGND1
MGR030
-
7 DIAG
OVERRULE
Fig.9 Stereo bridge-tied load application (SOT418-2).
1999 Apr 08
16
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
handbook, full pagewidth
1000 F (16/40 V) VP1 18 220 nF IN1 2 60 k VP2 13
100 nF
VP
-
V/I
VINL front
-
OA
+ +
17 OUT1
+ + TDA8586TH
n.c. 1 60 k V/I
- -
VPn OA 19 HVP1
4 or 8
-
+
+ -
OA 20 OUT2
4 or 8
220 nF VINL rear
IN2 3 60 k
+ +
V/I
-
- -
220 nF VINR front
IN3 4 60 k
V/I
-
OA
+ + +
14 OUT3
ACREF 6 47 F (10 V) VPn 30 k 60 k
+ -
4 or 8
V/I
-
VPn OA
-
12 HVP2
+
+ -
OA 11 OUT4
BUFFER 220 nF VINR rear switched +9 V 30 k MSO 8 IN4 5 60 k
4 or 8
+ +
V/I
-
+5 V 10 k
-
7 DIAG
INTERFACE 10 9 OVERRULE 15
DIAGNOSTIC 16 PGND1
15 k switch 4.7 F (10 V)
MGR031
DDDSEL
PGND2
Fig.10 Quad single-ended application (SOT418-2).
1999 Apr 08
17
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
INTERNAL PIN CONFIGURATION PIN TDA8586TH 2, 3, 4, 5 and 6 NAME inputs
handbook, halfpage
TDA8586
EQUIVALENT CIRCUIT
VP
IN
MGE014
11, 12, 14, 17, 19 and 20
outputs
handbook, halfpage
VP
OUT
0.5 VP
MGE015
8
mode select
handbook, halfpage
VP
MGE016
1999 Apr 08
18
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
PACKAGE OUTLINES DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)
TDA8586
SOT243-1
non-concave D x Dh
Eh
view B: mounting base side
d
A2
B j E A
L3
L
Q c vM
1 Z e e1 bp wM
17 m e2
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT243-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A 17.0 15.5 A2 4.6 4.2 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 2.54 e1 e2 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.4 x 0.03 Z (1) 2.00 1.45
1.27 5.08
ISSUE DATE 95-03-11 97-12-16
1999 Apr 08
19
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
TDA8586
HSOP20: heatsink small outline package; 20 leads; low stand-off
SOT418-2
E D x
A X
c y E2 HE vM A
D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 20 Z e bp 11 wM (A3) A 10
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1.27 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.5 2.0 8 0
+0.12 0.53 0.32 16.0 13.0 -0.02 0.40 0.23 15.8 12.6
0.25 0.25 0.03 0.07
Note 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT418-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-10-29 98-02-25
1999 Apr 08
20
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Surface mount packages REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 1999 Apr 08 21 MANUAL SOLDERING
TDA8586
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
Suitability of IC packages for wave, reflow and dipping soldering methods
TDA8586
SOLDERING METHOD MOUNTING PACKAGE WAVE Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount BGA, SQFP HLQFP, HSQFP, HSOP, HTSSOP, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. suitable(2) not suitable not not not suitable(3) recommended(4)(5) recommended(6) suitable REFLOW(1) - suitable suitable suitable suitable suitable - - - - - DIPPING suitable
1999 Apr 08
22
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and auto BTL/SE selection
NOTES
TDA8586
1999 Apr 08
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/750/02/pp24
Date of release: 1999 Apr 08
Document order number:
9397 750 05483

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